| Summary: | 博士 === 國立交通大學 === 電子研究所 === 101 === The channel coding module with high computation load plays an important role in wireless communication system. The competitive design must not only meet the system requirements in high throughput but also improve the energy efficiency. In the past decade, LDPC block codes (LDPC-BCs) are widely adopted in communication specifications for excellent error-correcting performance and high throughput. However, the state-of-the-art designs of LDPC-BC decoders show their weakness for providing flexible code-rates and variable codeword length. Contrarily, the LDPC convolutional codes (LDPC-CCs) combine the excellent error-correcting performance similar to LDPC block codes and variable data frame size similar to convolutional codes. But the drawbacks of LDPC-CC include the long decoding latency, low parallelism, and low to medium decoding throughput. How to achieve over Gbps throughput and to reduce the power consumption are still difficult to LDPC-CC decoder design. Accordingly, this dissertation investigates both LDPC-BCs and LDPC-CCs to explore the potential for higher throughput and better energy efficiency.
For LDPC-BCs, an (2048, 1920) irregular LDPC code is generated by proposed CP-PEG algorithm with better performance than other PEG-based codes; however, the large check node degrees introduced by high code-rate 15/16 become the implementation bottleneck. To design such a high code-rate LDPC decoder, our approach features variable-node-centric sequential scheduling to reduce iteration number, single pipelined decoder architecture to lessen the message storage memory size, as well as optimized check node unit to further compress the register number. Overall 73% message storage memory is saved as compared with traditional architecture. Fabricated in 90nm 1P9M CMOS technology, the test chip of LDPC-BC decoder could achieve maximum 11.5Gbps throughput under 1.4V supply voltage with core area of 2.7 × 1.4 mm^2. The energy efficiency is only 0.033 nJ/bit with 5.77 Gb/s at 0.8V to meet IEEE 802.15.3c requirements.
For LDPC-CCs, a (491,3,6) time-varying LDPC-CC decoder chip is implemented. The proposed design combines the algorithm level, node level, and bit level optimizations to achieve over 2Gb/s throughput with acceptable hardware cost and power. The algorithm level optimization is the on-demand variable node activation scheduling with concealing channel values, which can not only achieve twice faster decoding convergence speed than log-belief propagation (log-BP) algorithm but also reduce the 17% message storage capacity. The node level optimization duplicates the check node units and variable node units and unfolds the message storage FIFOs so that the throughput becomes twelve multiplying with clock frequency. In the meantime the bit level optimization is employed to retime the critical path such that the higher clock frequency can be achieved and message storage size is slightly reduced. Furthermore, a novel hybrid-partitioned FIFO is proposed to provide sufficient memory bandwidth to processing units and alleviate power consumption. With these schemes, a test chip of proposed LDPC-CC decoder has been fabricated in 90nm CMOS technology with core area of 2.37 × 1.14 mm^2. Maximum throughput 2.37Gb/s is measured under 1.2V supply with energy efficiency of 0.024nJ/bit/proc. Depending on the operation mode, power can be scaled down to 90.2mW while maintaining 1.58Gb/s at 0.8V supply.
Eventually these two works provide good features covering hundreds Mbps to several Gbps throughput range, flexible code rates, adjustable frame size, excellent performance, and better hardware/power efficiency. The proposed methodologies would make LDPC codes more competitive to the other error-control codes.
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