The Random Trap Induced Fluctuations of Bulk Tri-gate Devices by a New Trap Profiling Technique

• Main Authors: Tsai, Hanmin, 蔡漢旻
• Other Authors: Chung, Steve S.
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/51686493784587434320

碩士 === 國立交通大學 === 電子研究所 === 101 === As device channel length continues to scale beyond 100nm, we need to overcome many problems such as short channel effect, performance enhancement, and leakage current. So far, the major challenges have been overcome by difference technologies. For example, the short channel effect is solved by ultrathin junction depth and strained silicon device is used to enhance the electrical performance. While the variation properties induced by the discrete dopants and traps fluctuates the electronics properties significantly in the channel which lead to the mismatches of threshold voltage (Vth) and drive current. In this thesis, we proposed a new mechanism, called Random Trap Fluctuation (RTF), which was considered to be another important issue for the devise after the long term stress. It varies with the devise after the stress, e.g., Hot Carrier Stress (HC) or Negative Bias Temperature Instability (NBTI). Also, it was observed that RTF is the major fluctuation source after the stress. But, the understanding of the real mechanisms and phenomena of oxide (or interface) traps induced Vth fluctuation has been very difficult and rare has been reported so far. In this thesis, we developed a newly technique, called Random Trap Profiling (RTP), to profile the stress-induced traps. Compared to the conventional lateral profiling technique of trap, Charge-pumping Profiling, RTP shows its advantages for applications to single and very small devices and very suitable for ultra-scaled 3D devices, such as FinFET or Trigate. In this thesis, we used this new random trap profiling technique to identify the oxide trap position after the stress for a 28nm single-fin bulk trigate device and examine the physical mechanisms. As a consequence, several salient results can be drawn: (1) we successfully separated the fluctuation source from discrete dopant and the source from random traps after stress. (2) Two stress schemes, HC and NBTI, have been utilized to examine the trigate nMOS devices and trigate pMOS devices respectively. For trigate nMOS devices, the oxide traps are generated near the drain side after hot carrier (HC) stress; but for triage pMOS devices, they are generated more in the middle of the channel after NBTI stress. More importantly, (3) it has been found the reliability killer of advanced trigate devices should be the surface roughness on the side-wall and corner effect induced random traps either under the HC or NBTI stress, and the latter dominates the degradation of bulk trigate devices. These results will be helpful and valuable for the design of the next generation of bulk trigate CMOS devices beyond 20nm generation.