| Summary: | 碩士 === 國立交通大學 === 資訊科學與工程研究所 === 101 === In recent years, multiple-input multiple-output (MIMO) technology has been used widely in various communication systems. The main reason is that it can provide the efficiency and quality of data transmission. In addition, the orthogonal-frequency division multiplexing (OFDM) technology provides high-speed data transmission, as well as for operating in multipath over frequency selective fading channels, which has been adopted by many transmission systems. Therefore, the combination of these two technologies in next-generation wireless communication systems, MIMO-OFDM has become one of the most crucial technologies.
There are some topics in wireless communication development. First issue is algorithm verification platform development. Second issue is application-specific integrated circuit (ASIC) implementation for low-power design.
MIMO-OFDM system is very sensitive to the non-ideal front-end effects so need develop algorithms to solve them. However, only the development of algorithms without hardware to verify the algorithm is not valuable enough. In thesis we integrated a set of self-developed algorithm verification platform. This experimental platform integrated with field programmable gate array (FPGA), digital-to-analog converters (DAC), analog-to-digital converters (ADC), universal serial bus (USB) and radio frequency (RF) hardware module, combined with software graphical user interface (GUI), USB firmware, and comprises of MATLAB algorithms for solving non-ideal channel effects. The 4x4 MIMO-OFDM wireless communication system platforms are realized by combined with software and hardware co-design. Using this prototype platform makes the developed algorithms can accurate analysis and evaluate performance and verification.
On the other hand, power consumption is more and more important issue on ASIC implementation. Another part of thesis we propose a dynamic current scaling (DCS) mechanism to achieve low-power design. For example the DCS mechanism is applied to fast Fourier transform (FFT) processor to achieve the 40% power saving.
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