Backside Via Hole Process for Grounding GaAs HEMTs by Using ICP Dry Etching

• Main Authors: Wu, Ching-Feng, 吳青峰
• Other Authors: Chang, Edward-Yi
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/61271534951391544898

碩士 === 國立交通大學 === 材料科學與工程學系 === 101 === This study focuses on ICP dry etching optimization for via hole structure of GaAs/AlGaAs/InGaAs pHEMTs and investigation of grounding GaAs HEMTs. The etching process of the via hole structure for GaAs substrate was optimized to obtain ideal via hole profiles with flat bottom, smooth and slanted sidewall by ICP dry etcher with AZ-4620 photoresist etching mask. The etching condition was optimized with different ICP parameters such as coil power, pressure, platen power, total flow rate and flow rate ratio of etching gases Cl2 and BCl3. In addition, the influences of different parameters were also investigated. Etch rate can be increased with higher coil power, pressure and total flow rate. The smoothness of etch profiles can be enhanced apparently by reducing chamber pressure. An optimized ICP dry etching condition for the backside process of GaAs substrate had been obtained with 600 W coil power, 10 mtorr pressure and a Cl2 and BCl3 flow rate ratio of 3:1. After ICP dry etching process, the gold layer was electroplated on the sample with good continuity to act as a grounding plane. Afterwards, the devices were characterized by DC and RF measurements. The DC performances show no degradation after backside process. From the S-parameters measurement, the output inductance reduces from 520 pH to 380 pH after backside process. The cut-off frequency is increased from 32 GHz to 38 GHz and the maximum oscillation frequency is increased from 53 GHz to 57 GHz. Therefore, via hole grounding is proved to be an effective approach to improve RF performances.