Implementation of a layout context extractor for layout-dependent effects application
碩士 === 國立交通大學 === 電機學院電子與光電學程 === 101 === As CMOS process continuous scaling, both transistor’s gate width and gate length are on a scale of nano-meters. Thanks to the new process technologies, a single chip carries enormous amount of transistors. Those technological advances enable higher sophistic...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/95262683208273957554 |