Implementation of a layout context extractor for layout-dependent effects application

• Main Authors: Hung, Wei-Ming, 洪偉銘
• Other Authors: Chang, Kow-Ming
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/95262683208273957554

碩士 === 國立交通大學 === 電機學院電子與光電學程 === 101 === As CMOS process continuous scaling, both transistor’s gate width and gate length are on a scale of nano-meters. Thanks to the new process technologies, a single chip carries enormous amount of transistors. Those technological advances enable higher sophisticated system in the foreseeable future. On the other hand, they also lead to many layout proximity effects. The effects impact not only on transistor’s electrical characteristics, but also in device modeling, model extraction and circuit design flows. In this thesis, we discussed different types of layout proximity effect and also realized a layout context extractor. The extractor detected the transistor’s placement context and reported it back to the design circuit. It shortens design cycle and minimize the uncertainty gap between pre-layout and post-layout simulations. The extractor was validated by a 28nm analog design circuit with BSIM4.6 model and achieved less than 1% difference between pre-layout and post-layout simulations.