| Summary: | 博士 === 國立暨南國際大學 === 電機工程學系 === 101 === This thesis deals with the issues of DAC area and its power consumption in the high color-depth LCD driver ICs and proposes two novel architectures of DAC with a 10-bit resolution for LCD driver applications. The first proposed architecture, RFR-DAC, improves the linearity of DAC, unifies its channel performance, and achieves 10-bit resolution with a compact die size smaller than that of a conventional 8-bit RDAC. The proposed RFR-DAC combines a 6-bit RDAC and a 4-bit FR-DAC to offer unique two-voltage-selection and one-voltage-selection schemes without the need of unity-gain buffers to isolate parallel-connected resistor strings. A stacked floating class-AB control is also devised to bias the last output buffer stage. The 10-bit RFR-DAC prototypes are implemented using 0.35-μm CMOS technology with the worst DNL/INL = 0.11/0.92 LSB via a two-voltage-selection scheme; and 1.37/1.45 LSB via a one-voltage-selection scheme. The 10-bit RFR-DACs with two/one-voltage-selection schemes occupy only 70%/46% of the conventional 8-bit RDAC area.
The rest of this thesis presents a 10-bit low-power high-color-depth LCD column driver IC with two-stage multi-channel RDACs and switch resistance compensation. The design removes intermediate buffers from two-stage RDACs and uses global reference buffers to isolate the global resistor string and output channels. Because the global resistor string is isolated from output channels, the global resistor string can use a larger resistance value to achieve lower power consumption. This thesis proposes a class-AB buffer for the global reference buffers to compensate for the errors caused by the voltage drop on switches connected in series with the channel resistor string. The channel resistor strings also reuse the output stage current of the global buffer to reduce power consumption. Two prototypes, including a 15-channel DAC and a 396-channel column driver, were fabricated using 0.18-μm and 0.35-μm CMOS technologies, respectively, with the worst DNL/INL being 1.33/1.15 LSB and 0.55/1.36 LSB, respectively. The proposed 10-bit DAC implemented using 0.18-μm CMOS technology occupies only 66 % of the area of a conventional 8-bit RDAC using the same technology. The 396-channel column driver consumes a total static current of only 0.9 mA.
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