| Summary: | 碩士 === 國立成功大學 === 電腦與通信工程研究所 === 101 === A high isolation low noise amplifier (LNA) by using the transformer feedback to neutralize the Miller capacitance is implemented by a TSMC 0.18 μm CMOS process. High isolation and reduced chip size can be achieved. The measured results show that the gain is 10 dB, isolation is higher than 50 dB, noise figure is 5.2 dB, and the power consumption is 5.4 mW at 23 GHz. The chip size is 0.47×0.47 mm2.
A millimeterwave LNA using the LC tank to enhance the broadband operation implemented by a TSMC CMOS 90 nm process is proposed. The simulated results show that the gain is 16.1 dB, noise figure is 5.5 dB, and the power consumption is 10.2 mW from the RF bandwidth 54 to 67 GHz. The chip size is 0.5×0.5mm2.
To enhance the performance of phase noise and power consumption, the voltage controlled oscillator employing the body bias technology to couple the gate and body implemented by a TSMC 0.18 μm CMOS process is presented. Differential technology is also employed to improve the phase noise. The measured results show that the output power is 0.97 dBm, phase noise is -134.3 dBc/Hz, power consumption is 1.56 mW, and the figure of merit is -196.5 dBc/Hz from the RF bandwidth 4.91to 5.45GHz. The chip size is 0.6×0.6 mm2.
A miniaturized balanced-unbalanced circuit (balun) with second harmonic suppression is achieved by two coupled line and inductor implemented by a Transcom 0.25μm GaN HEMT process. The measured results show that the return loss is 10.3 dB, insertion loss is 4.5 dB, phase difference between two ports is 180°±2°, and the second harmonic suppression is as high as 50dB at 10 GHz. The chip size is 0.7×0.83 mm2.
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