| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 101 === Sub-threshold operation has been shown to be a promising approach for ultra-low power applications, such as portable mobile devices, biomedical electronic systems and wireless sensor network. However, operating logic circuits in the sub-threshold regime would seriously degrade the ratio of transistor driving current to leakage current and increase the sensitivity of process variations, thus increasing the possibility of logic functional failures. To increase the robustness of logic circuit in the sub-threshold regime, we propose a sub-threshold logic style called N-Critical Schmitt-Trigger logic. This structure could not only effectively increase the ratio of logic circuit driving current to leakage current, but also reduce the sensitivity of process variation when operated in the sub-threshold regime. In this thesis, the multiplier and accumulator (MAC) circuits are implemented in TSMC 90nm to demonstrate the feasibility of our proposed N-critical Schmitt-Trigger logic in the sub-threshold regime. According to post-layout simulation results, the MAC circuit implemented with our proposed logic structure shows 40% area overhead reduction and 6x energy-delay-product (EDP) improvement at 0.2V when compared with conventional Schmitt-Trigger logic structure[1].
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