FPGA and GPU Design Explorations of Nonlinear Signal Processing for RF Impairment Mitigation

• Main Authors: PingMa, 馬平
• Other Authors: Chih-Hung Kuo
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/99436355949322709604

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 101 === In this paper, we propose a complete mathematical model for a wide-range-CFO joint CFO and IQ imbalance compensation algorithm. The wide range of CFO is divided into three parts. According to the value of CFO, we have the Low-CFO Least-Square algorithm, the Least-Square algorithm, and the Short Preamble High-CFO Least-Square algorithm. By utilizing short preamble, the estimable range of CFO can be enlarged four times than only using short preamble and providing accurate estimate. Considering the hardware behavior when simulating the algorithm in C language, we apply High-Level Synthesis (HLS) to implement the algorithm on FPGA. We also apply Compute Unified Device Architecture (CUDA), one of the Graphic Processing Units (GPU), to accelerate the computing speed. Results show that our algorithm provides highly accurate estimate under very large range of CFO. HLS provides fast simulation in design phase.