Easily-Integrated and Energy-Efficient Design Techniques for Successive-Approximation Analog-to-Digital Converters

• Main Authors: Guan-YingHuang, 黃冠穎
• Other Authors: Soom-Jyh Chang
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/48k2gu

博士 === 國立成功大學 === 電機工程學系碩博士班 === 101 === This dissertation presents four circuit design techniques for successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the proof-of-concept prototypes, the proposed techniques are able to reduce the design overhead of the front-end and reference buffer and improve the ADC performance. The proposed techniques and their associated chip measurement results are sketched as follows: The first technique is to develop a low input capacitance architecture for SAR ADCs. A 10-bit prototype is fabricated in 0.13-um CMOS process. Compared with conventional successive approximation ADCs, the proposed ADC can reduce the input capacitance to 1.2 pF for 10-bit resolution. At 12 MS/s and 1.2-V supply, this ADC consumes 0.32 mW and achieves an SNDR of 50.89 dB, resulting in a figure of merit (FOM) of 95 fJ/conversion-step. The second technique is a power efficient switchback switching method for a 10-bit 30-MS/s SAR ADC. With respect to the monotonic switching method, the proposed switching method can reduce the input common-mode voltage variation, which improves the dynamic offset and the parasitic capacitance variation of the comparator. In addition, the switchback switching method does not consume any power at the first DAC switching, which can reduce the power consumption and design effort of the reference buffer. The prototype was fabricated in 90-nm 1P9M CMOS technology. At 1-V supply and 30 MS/s, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 56.89 dB and consumes 0.98 mW, resulting in a FOM of 57 fJ/conversion-step. The third technique presents a bypass window SAR ADC for biomedical applications. To reduce energy consumption, a bypass window technique is used to select switching sequences to skip several conversion steps when the signal is within a predefined small window. The power consumptions of the capacitive DAC, latch comparator, and digital control circuit of the proposed ADC are lower than those of a conventional SAR ADC. The proposed bypass window tolerates the DAC settling error and comparator voltage offset in the first four phases and suppresses the peak DNL and INL values. A proof-of-concept prototype was fabricated in 0.18-um 1P6M CMOS technology. At 0.6-V supply voltage and 200-kS/s sampling rate, the ADC achieves a SNDR of 57.97 dB and consumes 1.04 uW, resulting in a figure of merit of 8.03 fJ/conversion-step. The ADC core occupies an active area of only 0.082 mm2. The fourth one, which combines the bypass window and the direct switching techniques, is manipulated to develop a high speed SAR ADC. The bypass window technique can tolerate the incomplete settling error of the DAC without any extra comparison cycle and the direct switching technique can reduce the digital circuit delay. The prototype was fabricated in 40-nm 1P9M CMOS technology. At 0.9-V supply voltage and 200-MS/s sampling rate, the ADC achieves a SNDR of 57.16 dB and consumes 818 uW, resulting in a figure of merit of 13.9 fJ/conversion-step. The ADC core occupies an active area of only 0.013 mm2.