Layout Generator for Symmetric Analog Circuits

• Main Authors: Chung-LinLee, 李宗霖
• Other Authors: Jai-Ming Lin
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/92033662672784934209

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 101 === In past few years, analog design automation has attracted more attention, and many researches have been published. Most of them focus on placement of analog blocks without considering routing issues. Recently, some papers start to consider routability-driven placement in analog circuits. However, their models used to estimate routing congestion are based on approaches for digital circuits, which make routing paths estimated by their models not match to real routing paths. Hence, this thesis proposes a shortest path estimation model to predict routing channels between any two modules during placement stage. Moreover, DRC rules are considered in placement methodology in order to obtain legal layouts. In addition to placement, a routing methodology used to route nets, which include signal nets and power nets, is proposed. We actually implement the design flow as a tool. The experimental results show our tool can generate layouts efficiently. More importantly, our tool gets better results in term of area and wirelength in all test cases comparing to the method which uses the bounding box estimation method.