Design of a Contention-aware Hybrid On-Chip Memory Management Mechanism
碩士 === 國立成功大學 === 資訊工程學系碩博士班 === 101 === Scratchpad memories (SPM) have been increasingly used in embedded system due to their higher energy and area efficiency compared to ordinary caches. Hybrid on-chip memory architecture that combines SPM with a mini cache is also proposed. In order to reduce of...
Main Authors: | Yu-ShiangChien, 錢郁翔 |
---|---|
Other Authors: | Da-Wei Chang |
Format: | Others |
Language: | en_US |
Published: |
2013
|
Online Access: | http://ndltd.ncl.edu.tw/handle/54741457670164006147 |
Similar Items
-
Data Access Behavior Aware Online Allocation in an Innovative Hybrid On-Chip Memory
by: Bo-HanWu, et al.
Published: (2013) -
Thermal-aware Memory System Design Automation Method for Multi-Processor System-on-Chips with 3D-stacked Hybrid Memories
by: LIU, CHIA-YIN, et al.
Published: (2018) -
Core-characteristic-aware off-chip memory management in a multicore system-on-chip
by: Jeong, Min Kyu
Published: (2013) -
Design of a Low-power Content Addressable Memory with Current Self-adjusted Mechanism
by: Yung-Shiang Lin, et al.
Published: (2009) -
Hybrid Network-on-Chip: An Application-Aware Framework for Big Data
by: Juan Fang, et al.
Published: (2018-01-01)