Design of a Contention-aware Hybrid On-Chip Memory Management Mechanism

• Main Authors: Yu-ShiangChien, 錢郁翔
• Other Authors: Da-Wei Chang
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/54741457670164006147

碩士 === 國立成功大學 === 資訊工程學系碩博士班 === 101 === Scratchpad memories (SPM) have been increasingly used in embedded system due to their higher energy and area efficiency compared to ordinary caches. Hybrid on-chip memory architecture that combines SPM with a mini cache is also proposed. In order to reduce off-chip memory access in hybrid on-chip memory architecture, some related works put the most frequently accessed data into SPM. However, these methods may be ineffective because the most frequently accessed data may be not the main cause of off-chip memory access. Instead, off-chip memory accesses are caused by cache miss, and reducing cache misses can reduce off-chip memory accesses. Therefore, in this work, we propose using cache miss as a criterion to determine whether a page should be moved to SPM. We propose a page miss bookkeeping circuit to calculate the number of cache misses happened in a page. When the number of misses in a page is higher than a threshold, the page is moved to SPM. Compared to cache on-chip memory architecture, experimental results show our method can reduce the energy delay production (EDP) by 49%. Compare to the work in [19], our method can reduce the EDP by 26%.