Analysis of Status Variable Identifications for Semiconductor Fabrications

• Main Authors: Chih-ChiaLi, 李知珈
• Other Authors: Yeu-Shiang Huang
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/25596120097670915062

碩士 === 國立成功大學 === 工業與資訊管理學系碩博士班 === 101 === Owing to the developement of information technology and the increase of the demand of smart phones and mobile devices, the global semiconductor market has been grown fast which results in intensive competition. Thus, decreasing the risk of manufacturing processes has become essential factors. There are thousands of complicated sequential steps in the semiconductor manufacturing process, and even one abnormal step in chambers could lead to yield loss, which makes the abnormality of process a serious issue. This study analyzes the Status variable identifications (SVID) which are collected from the Fault Detection and Classification (FDC) system in one of the fabrications, and utilizes these data to evaluate states of the production equipment. This study uses the Hampel identifier outlier detection method in which various etching processes with the equipment parameters data are combined into a single index, to detect abnormal chambers among numerous etching ones. The aim of this study is to use the collected data to determine the appropriate preventive maintenance (PM) schedule for equipments, which can raise the yield rate of the manufacturing process. In addition, this study investigates the proper parameters setting to anticipate better wafer quality during the etching process by using the multi-group discriminant analysis. We validated the proposed method with a field empirical study, and the results demonstrate the practical viability of this approach. This approach can assist engineers in actively noticing the proper setting of chamber parameters and distinguishing the abnormal chambers during the etching process.