Low-Complexity Chip Design of carrier frequency offset estimation and compensation for Body Area Network Transceiver Systems

• Main Authors: Wei-Hao Chiu, 邱威豪
• Other Authors: Kuang-Hao Lin
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/03856478687321306100

碩士 === 國立勤益科技大學 === 電子工程系 === 101 === This work presents a synchronization architecture based on ZigBee physical layer specifications for body area network systems. It uses preambles for correlation operation to detect the front-end of symbols and then calculate the influence of channel effect, for example, carrier frequency offset (CFO). By using the crosscorrelation and auto-correlation architectures as the synchronization of receivers, the data which is influenced by the carrier frequency can be compensated with the CFO compensation structure. This paper uses system simulation for signal compensation of the transmitting and receiving ends, which can detect the CFO bias radian correctly, with a detection error less than 10-3, and CFO is therefore compensated. The proposed hardware architecture with high precision is simulated and implemented by TSMC 0.18um CMOS technology. The design gate count and chip area are about 81k and 1.878mm2, respectively.