Design of Scan Architecture Targeted for Test Input/Output Compaction

Design of Scan Architecture Targeted for Test Input/Output Compaction

碩士 === 國立中興大學 === 資訊科學與工程學系 === 101 ===

Bibliographic Details
Main Authors: Che-Wei Kao, 高哲緯
Other Authors: 王行健
Format: Others
Language:zh-TW
Published: 2013
Online Access:http://ndltd.ncl.edu.tw/handle/50654158691508571245
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spelling ndltd-TW-101NCHU53940362017-01-14T04:15:06Z http://ndltd.ncl.edu.tw/handle/50654158691508571245 Design of Scan Architecture Targeted for Test Input/Output Compaction 可提升輸入及輸出壓密演算法效能的掃描鍊架構設計 Che-Wei Kao 高哲緯 碩士 國立中興大學 資訊科學與工程學系 101 王行健 2013 學位論文 ; thesis 35 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 國立中興大學 === 資訊科學與工程學系 === 101 ===
author2 王行健
author_facet 王行健
Che-Wei Kao
高哲緯
author Che-Wei Kao
高哲緯
spellingShingle Che-Wei Kao
高哲緯
Design of Scan Architecture Targeted for Test Input/Output Compaction
author_sort Che-Wei Kao
title Design of Scan Architecture Targeted for Test Input/Output Compaction
title_short Design of Scan Architecture Targeted for Test Input/Output Compaction
title_full Design of Scan Architecture Targeted for Test Input/Output Compaction
title_fullStr Design of Scan Architecture Targeted for Test Input/Output Compaction
title_full_unstemmed Design of Scan Architecture Targeted for Test Input/Output Compaction
title_sort design of scan architecture targeted for test input/output compaction
publishDate 2013
url http://ndltd.ncl.edu.tw/handle/50654158691508571245
work_keys_str_mv AT cheweikao designofscanarchitecturetargetedfortestinputoutputcompaction
AT gāozhéwěi designofscanarchitecturetargetedfortestinputoutputcompaction
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AT gāozhéwěi kětíshēngshūrùjíshūchūyāmìyǎnsuànfǎxiàonéngdesǎomiáoliànjiàgòushèjì
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