| Summary: | 碩士 === 逢甲大學 === 通訊工程學系 === 101 === This study mainly researches the front-end CMOS RFICs in receiver. Several circuits are presented in this study. They include a dual band low noise amplifier (LNA) which is applied at 2.4/5.2 GHz, a mixer and two voltage controlled oscillators (VCOs) which are primarily designed for direct broadcasting satellite. These chips are implemented by using Taiwan Semiconductor Manufacturing Company (TSMC) CMOS 0.18 process. The advantages of TSMC process primarily high-frequency circuit process, are low-cost, high yield and high integration.
The LNA uses an original design methodology that helps selecting input/output matching network element values. In this study, current-reused structure is used that input signal can be amplified twice without increasing the overall power consumption. The designed LNA achieves gains of 16 dB/13 dB and noise figures of 3.6 dB/4.7 dB at 2.4 GHz/5.2 GHz respectively with 1.5 V supply voltage and 10.8 mW power consumption. The total chip area is 0.64mm2.
In the mixer design, Gilbert Cell and dynamic current injection technology are adopted as circuit architecture. This study, the traditional Gilbert Mixer structure is improved by using the active load instead of the passive load to increase the conversion gain, and use dynamic current injection technology to decrease flicker noise. The simulated results show that the mixer has a conversion gain of 14.63 dB, P1dB of -16 dBm and DSB noise figure of 7.7 dB. The power consumption (with buffers) in the 1.8 V supply voltage is 6.93 mW. The total chip area is 0.49 mm2.
Finally, two VCOs are presented. In the first VCO (VCO1), we use Colpitts oscillator as the circuit architecture. The output inductor and capacitor combination as Bias-Tee buffer. The advantages are low phase noise, high output power and good integration. The simulated results show the oscillation center frequency of 13 GHz with the phase noise of -114.5 dBc/Hz at 1 MHz offset. The power consumption (with buffers) is 32.9 mW and tuning range is 3.85 %. The total chip area is 0.42 mm2.
The second VCO (VCO2), a low-voltage, low-power and high-performance VCO is presented. Forward-body biased technique is utilized in this VCO for threshold voltage (Vt) reduction, leading to a reduced supply voltage and minimized dc power consumption. The proposed VCO can operate at a 0.53 V low supply voltage and consume 1.2 mW low core power. Under this condition, the simulated phase noise of the VCO is −111.76 dBc/Hz at 1 MHz offset from a 13 GHz carrier and tuning range is 7.69%. The calculated figure of merit (FOM) of VCO2 is -193.25 dB/Hz, which is much better than VCO1. The total chip area is 0.49 mm2.
|
|---|
