An Integer Linear Programming Approach to Large Scale 3D VLSI Incremental Floorplanning

• Main Authors: Fong-Shou Liang, 梁峰碩
• Other Authors: Jong-Sheng Cherng
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/72627384803603372638

碩士 === 大葉大學 === 資訊工程學系碩士班 === 101 === As the circuit modules need small changes of their locations and functions in a floorplan, incremental floorplanning is proposed to improve the floorplan quickly. In this thesis, Mathematical programming approach is used to solve the incremental floorplanning problem for large scale VLSI circuits to achieve layout optimization and shorten floorplanning time. It has better performance in solving incremental floorplanning for small scale VLSI circuits by using integer linear programming(ILP), however, as circuit function growing, chip area becomes larger, it is time-consuming for solving large scale VLSI incremental floorplanning problem by using ILP approach directly due to lots of constraints and variables. Therefore, the divide and conquer strategy is proposed to divide a VLSI circuit into some subcircuits, and the incremental floorplanning problem of each subcircuit is then solved by ILP efficiently. After each subproblem is conquered, merging procedures are applied to complete the whole incremental floorplanning problem.