| Summary: | 碩士 === 朝陽科技大學 === 資訊與通訊系碩士班 === 101 === In recent year, high speed circuit such as voltage control oscillator (VCO) and dual-modulus prescaler in the face of vital design challenge. In previous divider designs dissipated over 40~50% power consumption in frequency synthesizers. Accordingly, we investigated conventional divider designs and presented a frequency divider with asynchronous circuit structure. This thesis presents both an extended true-single-phase-clock (E-TSPC) and true-single-phase-clock (TSPC) based high frequency divide-by-4/5 divider design for low supply voltage and low power dissipation applications. First, we use TSMC CMOS 1P6M 0.18μm process technology to implement the frequency divider circuit. By using asynchronous circuit scheme, the proposed design significantly reduces power consumption due to lower switching activity. And the third D flip-flops (DFF) hire true-single-phase-clock (TSPC) architectures to achieve lower short circuit power. Post layout simulation results show that when compared with recently design as much as 51% in power consumption and 53% in power-delay-product can be achieved by the proposed design. Finally, the proposed design has been implemented with a 0.18μm CMOS technology. When the supply voltage is 1.8V, the measured operation speed of the proposed divider reaches up to 5.6GHz with power consumption 0.88mW.
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