| Summary: | 碩士 === 朝陽科技大學 === 資訊工程系碩士班 === 101 === A closed-loop scheme of High-Gain Switched-Inductor-Switched- Capacitor-Based Step-Up DC-DC Converter is proposed by using a phase generator and pulse-width-modulation-based(PWM-based) gain compen- sator for step-up DC-DC conversion and regulation. In the power part of SISCC there are two cascaded stages including: (i) pre-stage: a two-stage serial-parallel switched-capacitor (SC) circuit, and (ii) core-stage: two switched-inductor (SI) resonant boosters in parallel. In the pre-stage SC circuit, it provides at most 3 times voltage of source Vs for supplying the rear boosters. In the core-stage SI boosters, the step-up gain can reach to 2/(1-D), where D means the duty cycle of the MOSFET in SI. Theoretical this SISCC can boost the output voltage Vo to 16 times when D= 0.67. Further, the PWM technique is adopted not only to enhance the output regulation for the compensation of the dynamic error between the practical and desired outputs, but also to reinforce output robustness against source or loading variation. Finally, the closed-loop SISCC is designed by OrCAD SPICE and simulated for some cases: steady-state and dynamic response (source/loading variation). All results are illustrated to show the efficacy of the proposed scheme.
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