Design and Implementation of Interleaved Class DE Resonant Converter with Synchronous Rectification

• Main Authors: Wei-Shi Lo, 羅瑋錫
• Other Authors: Li-Ming Wu
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/82672963521083517848

碩士 === 健行科技大學 === 電機工程所 === 101 === This thesis deals with the analysis and implementation of interleaved Class DE resonant converter with synchronous rectification. The proposed converter consists of Class D resonant inverter at the front end and Class E rectifier at the rear end. Based on inductive load and modular design, the converter is configured to operate with two modules interleaved in parallel and synchronized in rectification. Advantages of such a converter include simple structure, high efficiency, high power density, low output ripple, and better cost effectiveness. To account for converter control, L6599 as the frequency modulation IC to regulate the output voltage and IR1168 as the self-driving synchronous rectifier to enhance converter efficiency have been used. Except theory, design and simulation, two prototype converters with rating 180W/19V/9.4A, one has interleaved structure and the other has not, are constructed respectively for performance comparison. The remedy to mitigate the ringing effect caused by parasitic elements in the class E rectifier is proposed and discussed. As a result, the experimental measurements find good agreements with theory anticipation. Zero voltage switching is realized in full load range. With the ringing effect being eliminated moderately, the converter maximum efficiency is found to be 92.8% at the 80% load.