Implementation of a CountMin Sketch Update Controller on the NetFPGA10G Platform
碩士 === 中原大學 === 通訊工程碩士學位學程 === 101 === It’s a challenging task to conduct accurate measurement in wire-speed for high speed computer networks. This dissertation implements sets of counters based on the Count-Min Sketch with two-level memory hierarchy in the Xilinx Virtex-5 TX240T FPGA on a NetFPGA-1...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/25220568593760629099 |
| Summary: | 碩士 === 中原大學 === 通訊工程碩士學位學程 === 101 === It’s a challenging task to conduct accurate measurement in wire-speed for high speed computer networks. This dissertation implements sets of counters based on the Count-Min Sketch with two-level memory hierarchy in the Xilinx Virtex-5 TX240T FPGA on a NetFPGA-10G platform. We focus on the design interfacing banks of QDRII SRAMs such that Count-Min sketch data structure can be stored and processed by the host processor for various observed time intervals. The design space is explored and verified with real-world traces.
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