Downlink-LTE-Based Transceiver Implementation by Using Software-Hardware Co-Simulation

• Main Authors: Po-Hao Chang, 張博豪
• Other Authors: Rih-Lung Chung
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/63845361040217816705

碩士 === 中原大學 === 通訊工程碩士學位學程 === 101 === In this thesis, we employ the hardware-software co-simulation scheme to implement some critical blocks of the LTE downlink transceiver in the frequency division duplexing (FDD) mode. We adopt the Simulink® and System Generator® tools for rapid prototyping the system. We first program the MATLAB codes of each building block and simulate each block function as for design reference. Then, we simulate each and whole system blocks by using System Generator®. In the transmitter, we design a packet control circuit in the LTE’s transmitter end to generate control signal of the transmitted signal frame. We then implement pseudo-noise binary generator and quadrature-phase-shift keying (QPSK) symbol-mapping circuits, and use the inverse fast-Fourier transform (IFFT) module of the System Generator® to generate orthogonal frequency-division-multiplexing (OFDM) signal. In the channel end, we use the multipath fading channel module for generating frequency-selective channel. In the receiver end, we implement packet detection module and fractional carrier frequency offset estimation and correction modules, for timing and frequency synchronizations. Next, we implement DFT-based channel estimator module and use the FFT module for realizing the downlink LTE’s demodulator. Finally, for hardware verification, we transfer the LTE’ transmitter and receiver into bitstream files by using the ISE design suite, and download the file on the WARP software defined radio platform to verify the correctness of the downlink LTE-based system.