The Minimization of Compensated Delay for Multi-Voltage Clock Tree Designs
碩士 === 中原大學 === 電子工程研究所 === 101 === In modern VLSI designs, the minimization of power consumption is a very important issue. To minimize power consumption, the use of multiple voltages is a useful approach. However, in a multi-voltage design, the clock skew control becomes very complicated. Previous...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/3kb3k6 |