Architecture Explorations for Multi-Core Computer Systems

• Main Authors: Geng-Siao Lee, 李耕學
• Other Authors: Slo-Li Chu
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/76686526129175310784

博士 === 中原大學 === 電子工程研究所 === 101 === Because of the continuous evolution of computer technology, people have relied on high-performance computer systems to perform increasingly complex scientific computations (e.g., cancer genome sequencing). Although research results relating to diseases should be obtained as soon as possible, relevant programs typically require a considerable amount of time to process abundant input data or complex mathematical calculations to yield the desired results. The processing time of these programs can only be reduced by increasing the overall performance of computer systems. Because computer systems depend on processors for system control and program execution and computations, improving the processor architecture can significantly reduce the processing time of computer systems. Two common methods for increasing the processing speed are: 1) Improving the architecture of the solo processor: The influence of integrated circuit fabrication processes on the hardware performance has declined; thus, enhancing processor architectures can significantly reduce program processing time. 2) Developing high-performance interconnection networks by integrating many processors: When high-performance interconnection networks are adopted to connect multiple processors to a multi-core system, parallel computing using multiple processors can increase the throughput of calculations or subroutines of scientific computations. To achieve the performance of a single processor, this dissertation proposes a novel very long instruction word (VLIW) processor, named Caliburn, capable of dynamic scheduling and instruction packing mechanisms. This dynamic instruction packing mechanism can effectively improve processor performance and solve the incompatibility between the VLIW instructions and native program instructions in traditional VLIW processors. Another objective of this dissertation is to design a high-performance interconnection network based on the improved processor architecture. The two proposed interconnection networks are the Self Similar Cubic (SSC) and Bagua Network (BN). The basic blocks that form the SSC interconnection network are cube, which extend interconnection networks using the self similar method. The proposed interconnection network exhibits a satisfactory performance per unit hardware cost. The design of Bagua Network focuses on the extendibility of interconnection networks appropriate for multi-core systems with numerous processors. In addition, to verify the feasibility of the proposed processor and interconnection networks, all hardware is molded using electronic system level design. The hardware feasibility has been verified by programming the Verilog hardware description language according to the specifications. Finally, the experimental results of Caliburn, SSC, and Bagua Network are discussed in the corresponding chapters.