| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 101 === In our thesis, we propose an extensible sorting hardware architecture circuit. Analyzing the repetition of the Odd-Even Transposition Sort method, we design a basic sorting cell by the hardware description language. We can apply several basic sorting cells to build as the extensible sorting hardware circuit and satisfy the required input numbers of the sorting data. The extensible sorting hardware circuit can be applied to the FlexRay communication controller circuit for adjustment of the several cases of the sorting input data numbers. FlexRay is a specification of vehicle network communication which provides high speed, timing trigger, and fault tolerance. In our thesis, we also implement the circuit of the FlexRay communication controller with the Verilog hardware description language. We demand a sorting circuit to sort the timing table data in the communication controller circuit to correct the global time. The basic sorting cell circuit can be re-used and convenient to other applications. The sorting circuit has a function to save energy by turning off the not-use modules. Finally, we verify the circuit of communication controller to simulate and synthesize the circuit on the FPGA. We experiment the field try to confirm our design of the communications controller and extensible sorting circuit working correctly.
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