| Summary: | 碩士 === 長庚大學 === 資訊工程學系 === 101 === Modern IC design techniques and wireless network techniques drive explosive developments in the embedded computing, personal computing, and pervasive computing etc. Many “smart” products, e.g., smart phones, game boxes, vehicle information systems, are also proposed in an amazing time-to-market speed. To satisfy the quality of services for these products, chip makers have adopted the multi-core architecture in their microprocessor designs. The trade-off between the processor performance and the energy consumption, therefore, become the most important issues in chip design. Many conventional researches have proposed the task scheduling algorithms with the Dynamic Voltage Scaling (DVS) mechanism to solve the energy consumption problem. Most of their approaches, however, focus on scheduling periodic tasks. In most real time systems, in fact, periodic tasks and aperiodic tasks will exist simultaneously. Only a few studies have addressed this kind of mixed task set, but most of their discussions were limited in the single-core processor. In this paper, we will focus on designing an energy-saving task scheduling algorithm schedule the mixed task sets in multi-core systems. Our goal is to minimize the chip energy consumption to execute tasks but still satisfy their performance requirements. To achieve this goal, we propose a heuristic algorithm by taking full advantage of the cores’ idle time. We can apply the DVS mechanism and extend the execution time of tasks within a larger time space.
|
|---|
