| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 102 === The study of this thesis focuses on the design of injection-locked frequency divider and multiplier used in the phase lock loop of the wireless transceiver. All the proposed circuits are implemented by TSMC 0.18μm 1P6M CMOS process.
In this thesis, two wide locking range frequency dividers and one injection-locked frequency tripler is proposed. Based on the locking range formula, the strength enhancement of injection signal will make locking range wider. Following this concept, this thesis demonstrates new methods to intensify the strength of injection signal.
Compared to the published injection-locked frequency dividers, the injection-locked frequency dividers proposed in this thesis demonstrate simple and efficient method to enhance the injection strength with low power consumption. The locking range formula shows that it is difficult to maintain locking range with high output power. Therefore, the proposed ILFT demonstrates a new method achieving high output power with suitable locking range.
In chapter II, a low power consumption and wide locking range injection-locked frequency divider by three is realized. This proposed ILFD combines a direct injection-locked frequency divider by three and direct injection-locked frequency divider to achieve the divide-by-three mechanism. Furthermore, the even harmonic signal at the common source node of cross coupled pair is feedback to direct injection transistors. The injection current is enhanced with proposed structure. The measured locking range is from 11.2 GHz to 18.1 GHz (47.1%) with an injection power of 0dBm. The measured maximum output power is -3.1dBm with a tuning voltage of 2V. The power consumption of the core circuit takes 2.69mW from a 1.2V power supply.
In chapter III, a new method to produce the necessary third harmonic is demonstrated. The even harmonic signal at common source node of cross coupled pair is mixed with fundamental signal to generate the necessary third harmonic in divide-by-four frequency divider design. The measured locking range is from 20.8 GHz to 27.6 GHz (28.1%) with an injection power of 0dBm. The measured maximum output power is -0.4dBm with a tuning voltage of 2V. The power consumption of the core circuit takes 3.68mW from a 1 V power supply.
In chapter IV, a injection-locked frequency tripler by using mixing technique is demonstrated. This proposed ILFT uses a push-push oscillator to generate the even harmonic signal which is mixed with input signal. The conventional non-linear amplifier topology is replaced. The measured locking range is from 6.88 GHz to 9.12 GHz (28%) with an injection power of 0dBm. The measured maximum output power is -4.3dBm with a tuning voltage of 0V. The power consumption of the core circuit takes 4.2mW from a 1V power supply.
The simulation and measurement results proof that the division mechanism proposed in this thesis effectively enhance the locking range. In the future, it is a good extension to study how to intensify the mixing mechanism of injector.
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