| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 101 === In this thesis, there are different circuits to achieve low-power designs. In the case without reducing performance, reducing switching activities is adopted to further achieve low power consumption. We had achieved implemented a multichannel serial-to-parallel signal synchronizing circuit and multiplier-accumulator arithmetic circuits. Based on reducing switching activities, we proposed several low-power architectures to lower switching power.
Multichannel receivers which were implemented by two manners: one was using the cell-based design flow to finish the circuit synthesis, auto placement and routing, and the other one was using the mixed-signal design flow to implement the circuits. Upon completion of multi-channel synchronous receivers, we further developed some low-power designs and verify their functionality where portion of circuit blocks we proposed can save 22% of the power consumption. Using ramp waveform and delay control, the proposed architectures can further save 54% of the power dissipation.
In the arithmetic circuit design, we employ a dynamic range detection to control flip-flop and sign extension. Compared to the conventional architectures using array-form PPS unit which consists of carry-lookahead adders. Under the same architectural design, the proposed architectures can conserve at least 10% power consumption to perform the ADPCM audio coder and G.723.1 speech coder. When considering the products of the areas, critical delay and power consumption, the proposed architectures also outperform the conventional ones at the most cases.
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