| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 101 === This work presents the continuous-time delta sigma modulator for wide-band communication systems. The challenge of the wide-bandwidth continuous time delta sigma modulator is the clock jitter and excess loop delay. To solve excess loop delay problem, dual loop architecture is used to tolerate one clock period delay. However, with high sampling frequency (400MHz~1GHz) for wide-bandwidth applications and high resolution, excess loop delay is often more than one clock period and can make the loop filter unstable. The forecast architecture is proposed to extend the tolerance of the excess loop delay. A CT-ΔΣ modulator with 400 MHz sampling rate has been realized in a TSMC 0.18μm CMOS process, and SNDR 70.03dB in 10MHz bandwidth is achieved with 39.08mW power dissipation, the chip area is 1.721mm2.
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