| Summary: | 碩士 === 國立中正大學 === 資訊工程研究所 === 101 === Empirical mode decomposition (EMD) has outstanding performance in non-linear and non-stationary signal analysis. But it is not widely adopted in embedded and real-time signal processing applications due to its high computing complexity and high memory requirement. This thesis proposes a memory-efficient EMD design with parallel architecture, which has been integrated into an embedded system successfully. First, a memory-efficient segmented cubic spline computation is proposed to reduce the memory requirements in EMD. Then, a systematic exploration is proposed for the segment size & overlapped points of the segmented cubic spline, which affect computing time, quality and memory sizes. Finally, a scalable hardware architecture is proposed for our memory-efficient EMD. The above design techniques have been implemented and verified using FPGA and a real-time processing system has been demonstrated. Compared with the original approach, our proposed algorithm can reduce 95.3% memory in spline computations for 2,048-points EMD.
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