A Verification-aware Design Methodology for Thread Pipelining Parallelization on Stereoscopic Video Applications
博士 === 國立中正大學 === 資訊工程研究所 === 101 === This dissertation proposes a verification-aware design methodology that provides developers with a systematic and reliable approach to performing thread-pipelining parallelization on sequential programs. In contrast to traditional design flow, a behavior-model pro...
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ndltd-TW-101CCU003920162016-12-25T04:10:44Z http://ndltd.ncl.edu.tw/handle/41871175202510202155 A Verification-aware Design Methodology for Thread Pipelining Parallelization on Stereoscopic Video Applications 應用於立體視訊執行緒管線平行之驗證感知設計方法 Jian, Guo-An 簡國安 博士 國立中正大學 資訊工程研究所 101 This dissertation proposes a verification-aware design methodology that provides developers with a systematic and reliable approach to performing thread-pipelining parallelization on sequential programs. In contrast to traditional design flow, a behavior-model program is constructed before parallelizing as a bridge to help developers gradually leverage the technique of thread-pipelining parallelization. The proposed methodology integrates verification mechanisms into the design flow. To demonstrate the practicality of the proposed methodology, we applied it to the parallelization of a 3D depth map generator with thread pipelining. The parallel 3D depth map generator was further integrated into a 3D video playing system for evaluation of the verification overheads of the proposed methodology and the system performance. The results show the parallel system can achieve 33.72 fps in D1 resolution and 12.22 fps in HD720 resolution through a five-stage pipeline. When verifying the parallel program, the proposed verification approach keeps the performance degradation within 23% and 21.1% in D1 and HD720 resolutions, respectively. On the other hand, a thread-level superscalar-pipelining approach is also developed to parallelize the 3D video playing system. The parallel 3D video playing system can achieve a processing speed of 63.66 fps for HD720 resolution video. Guo, Jiun-In Chen, Peng-Sheng 郭峻因 陳鵬升 2013 學位論文 ; thesis 92 en_US |
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博士 === 國立中正大學 === 資訊工程研究所 === 101 === This dissertation proposes a verification-aware design methodology that provides developers with a systematic and reliable approach to performing thread-pipelining parallelization on sequential programs. In contrast to traditional design flow, a behavior-model program is constructed before parallelizing as a bridge to help developers gradually leverage the technique of thread-pipelining parallelization. The proposed methodology integrates verification mechanisms into the design flow. To demonstrate the practicality of the proposed methodology, we applied it to the parallelization of a 3D depth map generator with thread pipelining. The parallel 3D depth map generator was further integrated into a 3D video playing system for evaluation of the verification overheads of the proposed methodology and the system performance. The results show the parallel system can achieve 33.72 fps in D1 resolution and 12.22 fps in HD720 resolution through a five-stage pipeline. When verifying the parallel program, the proposed verification approach keeps the performance degradation within 23% and 21.1% in D1 and HD720 resolutions, respectively. On the other hand, a thread-level superscalar-pipelining approach is also developed to parallelize the 3D video playing system. The parallel 3D video playing system can achieve a processing speed of 63.66 fps for HD720 resolution video.
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author2 |
Guo, Jiun-In |
author_facet |
Guo, Jiun-In Jian, Guo-An 簡國安 |
author |
Jian, Guo-An 簡國安 |
spellingShingle |
Jian, Guo-An 簡國安 A Verification-aware Design Methodology for Thread Pipelining Parallelization on Stereoscopic Video Applications |
author_sort |
Jian, Guo-An |
title |
A Verification-aware Design Methodology for Thread Pipelining Parallelization on Stereoscopic Video Applications |
title_short |
A Verification-aware Design Methodology for Thread Pipelining Parallelization on Stereoscopic Video Applications |
title_full |
A Verification-aware Design Methodology for Thread Pipelining Parallelization on Stereoscopic Video Applications |
title_fullStr |
A Verification-aware Design Methodology for Thread Pipelining Parallelization on Stereoscopic Video Applications |
title_full_unstemmed |
A Verification-aware Design Methodology for Thread Pipelining Parallelization on Stereoscopic Video Applications |
title_sort |
verification-aware design methodology for thread pipelining parallelization on stereoscopic video applications |
publishDate |
2013 |
url |
http://ndltd.ncl.edu.tw/handle/41871175202510202155 |
work_keys_str_mv |
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