Summary: | 博士 === 元智大學 === 通訊工程學系 === 100 === Based on software defined radio (SDR) structure, the baseband circuits of the orthogonal frequency division multiplexing (OFDM) system and smart an-tenna are designed in the dissertation. It includes four major parts. A SDR channel simulator is designed in the first part for testing the base band trans-ceiver of various wireless communication systems. The proposed SDR archi-tecture and the hardware reconfiguration scheme are used to reconfigure the processing modules when the channel conditions are changed.
A SDR structure based carrier frequency offset (CFO) estimation and compensation circuit is designed in the second part for an orthogonal fre-quency division multiplexing (OFDM) system. The CFO circuit estimates and corrects frequency offset using the reconfigurable coordinate rotation digital computer (CORDIC) field programmable gate array (FPGA) rotation and vec-toring circuit modules. The required processing time and hardware reconfigu-ration function are our major design considerations. The experimental results demonstrate that the designed CFO estimation and compensation circuit im-plemented with FPGA chip can reduce the residual CFO to an acceptable range. Additionally, the designed CORDIC rotation and vectoring modules are programmable and reconfigurable so that they are also applicable for future SDR and cognitive radio applications.
The hierarchical multi-function matrix operation (MFMO) circuit modules are designed in the third part using CORDIC algorithm for realizing the inten-sive computation of matrix operations. The designed hierarchical MFMO cir-cuit modules can be used to develop a power-efficient SDR digital beam-former (DBF). The formulas of the processing time for the scalable MFMO circuit modules implemented in FPGA are derived to allocate the proper logic resources for the hardware reconfiguration. The hierarchical MFMO circuit modules are scalable to the changing number of array branches employed for the SDR DBF to achieve the purpose of power saving. The efficient reuse of the common MFMO circuit modules in the SDR DBF can also lead to energy reduction. Finally, the power dissipation and reconfiguration function in the different modes of the SDR DBF are observed from the experiment results.
A mobile surveillance system implemented with an embedded image cap-ture rotation platform and a Dedicated Short Range Communications (DSRC) transceiver is developed in the fourth part to real time monitor the remote en-vironments from a mobile terminal. The application programs of video capture and control are written in the ARM to acquire the 160×120 pixel pictures. The captured image data in a surveillance environment is transmitted to a remote mobile terminal through WiFi, Internet, PC server and DSRC transceiver. The DSRC baseband transceiver is implemented with the high speed DSP and FPGA based on reconfigurable structure. The two-ray Raleigh fading channel model and IEEE 802.11p DSRC channel model are used to test the perform-ance of the mobile surveillance system, respectively. The experimental results show that the bit error rate (BER) of the DSRC baseband transceiver operating in the time-varying fast fading channel meets the requirements specified in the DSRC specification.
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