The Design of Low Power RF Receiver for Ultra-wideband System and Array High Power Amplifier Using 0.18μm CMOS Process

• Main Authors: Chien-hua Lai, 賴建華
• Other Authors: Jeng-RernYang
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/12412980375048085067

碩士 === 元智大學 === 通訊工程學系 === 100 === This paper uses a TSMC 0.18 μm CMOS process to design a receiver for UWB systems. Three manufactures were commissioned to create the electric circuits 3~10GHz LNA, 3~10GHz mixer, and 2.4GHz power amplifier array. To achieve the goals such as a wide-band frequency, low power consumption, low noise figure, and high returns, the 3~10 GHz LNA adopts the current-reuse structure and utilizes a improved chebyshev and peaking inductor technology. The measurement results demonstrate the following performances of the design: The total power consumption is 7.52 mW under a 1.2 V supply voltage; the forward gain is 10±1.5 dB for a 3~10 GHz wideband frequency; the noise figure average (Min) is 3.9 dB; the input return loss is under -10dB, and the output return loss is under -12dB. Additionally, for the portion of the mixer that uses the folded-switching mixer with active balum for the low voltage supply, the forward gain is 22±0.5 dB for a 3~10 GHz wideband frequency; the noise figure(DSB) is 7.7~11.8 dB; the power consumption is 18.06mW; the IIP3 is -22dBm and the P1dB is-30dBm. 2.4GHz array of high power amplifier will combine all of the amplifier brings together the current. And the use of NMOS and PMOS between positive and negative signals into the save area of the driver stage, and this could make the whole area than traditional power amplifier combination of small. This circuit simulation result outpower power is 26dBm; the gain is11dB; the P1dB is 16dBm; the PAE is 15.4%; S11 is -18.7dB and S22 is -13.1dB.