The Optimum Method to Detect HDI PCB Fill Via Crack Problem - Design of Experiment
碩士 === 元智大學 === 工業工程與管理學系 === 100 === The consumer product trend achieve thin and small, but more func-tion requirement. PCB manufactures have to use ELIC(Every Layer In-terconnection) technology to satisfy customer needs. That means each via connected reliability in ELIC structure is all important....
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/24105391558791101766 |
| Summary: | 碩士 === 元智大學 === 工業工程與管理學系 === 100 === The consumer product trend achieve thin and small, but more func-tion requirement. PCB manufactures have to use ELIC(Every Layer In-terconnection) technology to satisfy customer needs. That means each via connected reliability in ELIC structure is all important. Then how to find out a optimum method to detect crack high risk issue is a big topic that we discuss.
First we choice thermal shock, thermal stress, reflow,three factors. To perform 23 factorial experiments to find out significant factor –Ther-mal stress. To perform one factor and 3 levels experiment to decide an optimum method and detect high risk via. This optimum condition: 260℃/ 20 second/ 5 cycle could effectively to detect filled via crack .This result can prevent the crack big issue to reveal to customer side and cause serious complain and reparation.
|
|---|