| Summary: | 碩士 === 國立雲林科技大學 === 電機工程系碩士班 === 100 === With the advancement in the semiconductor process technologies, the operating speed in the System-on-a-Chip is raised up to gigahertz. In this manner, the jitter performance of the synthesized clocks becomes more important. Most of the clock synthesizers adopt the techniques of phase-locked loop (PLL) and delay-locked loop (DLL). In order to improve the jitter performance, DLL is chosen as the main architecture of the proposed clock synthesizer in this thesis. DLL possesses several merits like the small jitter accumulation, the good system stability due to the first order system, and an on-chip capacitor to be integrated easily.
The diversity in the operating modes of the clock frequency is required inside the modern SoC chips. In the design of clock synthesizer base on DLL, the multiplication ratios are limited due to the architecture of DLL. The conventional architecture can only provide the multiplication ratios with the basic integral and half factors (1/2x, 3/2x, 5/2x…). In order to overcome its limitation, a new architecture is proposed in this thesis to achieve specific multiplication factors (15/14x, 13/12x, 13/8x, 13/6x, 8/3x, 13/4x, 15/4x). Furthermore, the new clock synthesizer can still provide integral factors (1x, 2x, 4x, 8x), half factors (3/2x, 5/2x, 7/2x, 13/2x, 15/2x) in addition to the specific multiplication factors. The multiplication factors of the new clock synthesizer extend to 18 choices. The programmable integral / fractional clock synthesizer based on DLL is designed and implemented in TSMC CMOS 0.18μm 1P6M process. The proposed clock synthesizer can accept the input clock with the frequency range from 170MHz to 300MHz and it can generate the output clock frequency within 170MHz~2GHz.
Key Word: delay-locked loop, clock synthesizer
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