| Summary: | 碩士 === 國立雲林科技大學 === 電機工程系碩士班 === 100 === Recently, there have been many researches for license plate recognition (LPR).
Many researches focus on the development of novel software programs in the computer
for improving varied algorithms. The major goal of the improvement is to enhance the
recognition rate for the license plate detection and character recognition.
In this thesis, we propose a fast algorithm for license plate detection which is
suitable for hardware implementation. A searching area with a fixed rectangular size is
applied to search the license plate. In the hardware design, we employ a special
architecture by using the memory banks and register banks to reduce the access times
for memory. A parallel architecture is applied for accumulating the pixels in both
vertical and horizontal directions to improve the searching performance. Once the
license plate has been detected, we use a parallel architecture with memory banks to
refine the license plate region. The design can increase the processing speed for
binarization and performs vertical and horizontal histogram processing in parallel.
In the implementation, the hardware architecture of our design was implemented by
using Verilog HDL. We used SYNOPSYS Design Vision to synthesize the design with
TSMC 0.13-μm cell library. It works with a clock period of 20 ns and can achieve a
processing rate of 50 Mpixels/second. The design is suitable for real-time applications
in the video resolution with 1280×960.
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