A High-Performance De-interlacing Hardware Design
碩士 === 國立雲林科技大學 === 電機工程系碩士班 === 100 === De-interlacing is an important topic in the field of television systems nowadays. The interlaced video is used to reduce the broadcasting bandwidth. Thus, a simple and efficient de-interlacing technique is necessary for real-time video applications. This thes...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/93289274420160592480 |
| Summary: | 碩士 === 國立雲林科技大學 === 電機工程系碩士班 === 100 === De-interlacing is an important topic in the field of television systems nowadays.
The interlaced video is used to reduce the broadcasting bandwidth. Thus, a simple and
efficient de-interlacing technique is necessary for real-time video applications.
This thesis proposed a novel de-interlacing algorithm for interlaced video. We
utilize a motion-direction detector to determine motion direction of block between the
adjacent images. A scene-change detector is used in our method to estimate if the main
body of block moves wildly. According to detection results from the motion-direction
detector, we choose temporal interpolation or spatial interpolation method to interpolate
the missing pixels. Experiment results show that our method is better than other
algorithms before. Moreover, we also design a high-performance seven-pipelined
architecture for our algorithm which can be used in many real-time applications.
Our technique is implemented with VLSI architecture by using Verilog HDL. The
system is designed with pipeline architectures to achieve better performance. We used
SYNOPSYS Design Vision to synthesize the design with TSMC 0.13μm cell library.
Synthesis results show that our design contains 50.8K gate counts. It operates with a
clock period of 5 ns and operates at a clock rate of 200 MHz.
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