Cache Utilization Aware Scheduling for Multi-core Systems
碩士 === 國立雲林科技大學 === 資訊工程系碩士班 === 100 === A chip multiprocessor (CMP) consists of several cores which can execute tasks independently. Due to the budget and chip area limit, last level cache is usually shared among cores. If tasks are running on different cores access the shared cache intensively and...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/73849918468142695946 |