| Summary: | 碩士 === 大同大學 === 電機工程學系(所) === 100 === Orthogonal Frequency Division Multiplexing (OFDM) has already been widely applied to various kinds of wireless communication system. In the OFDM systems, Fast Fourier Transform (FFT) processor is a module requiring high processing complexity. In this thesis, we propose a 128/64 point Fast Fourier Transform processor for WLAN applications. The processor can support 1-4 data paths computation. We choose the multiple-path delay commutator (MDC) architecture to design and implement. To reduce computational complexity, we choose mixed-radix algorithms that contain radix-2, radix-23 algorithms. The FFT processor has been implemented by using Verilog HDL, MATLAB and ModelSim for circuit design and simulation, respectively.
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