| Summary: | 碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 100 === Hereby I proposed to study a method, especially for digital communication systems which are operated above 10GT/s (40GT/s , 100GT/s…etc) rate with 5m~10m transmission distance, to optimize the setting of the communication IC’s equalizer faster and more efficiently. Nowadays, in the main frame of telecomm network, due to the high bit rate and the physical limit caused by the long transmission distance, we usually include equalizer into our circuit design to ensure a good signal quality. Still, how to set the equalizer’s tap coefficient is another critical factor for communication system. System engineers need to find out the optimized setting of the equalizer’s tap coefficient according to the architecture of the telecom IC’s equalizer against the property of communication channel which consist of paths in different lengths, connectors of different types, and cables. But because the architecture of equalizer is heavily related to silicon intelligent property, generally, the IC designers tend to give the mathematical model instead of the equalizer’s architecture to the system designers. Due to this limit for lack of clear and definite direction to find out the optimized setting of equalizer’s tap coefficient, system designers will take much more time to do a full sweep against all parameter but still fail to find out the optimized setting in a certain limited period. The method studied hereby, especially for designing equalizers with more tap coefficient, can have more advantage in time. For example, in a 4-bit equalizer optimization, using this method will be 27 times faster than a full sweep against all four taps of the equalizer.
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