A new hardware-efficient algorithm and reconfigurable architecture for image contrast enhancement

• Main Authors: Wen-Chieh Chen, 陳文杰
• Other Authors: Shih-Chia Huang
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/ws6ckf

碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 100 === Contrast enhancement is crucial when generating high quality images for image processing applications such as digital image or video photography, LCD processing, and medical image analysis. In order to achieve real-time performance for high-definition video applications, it is necessary to design efficient contrast enhancement hardware architecture to meet the needs of real-time processing. In this paper, we propose a novel hardware-oriented contrast enhancement algorithm which can be implemented effectively for hardware design. In order to be considered for hardware implementation, approximation techniques are proposed to reduce these complex computations during performance of the contrast enhancement algorithm. The proposed hardware-oriented contrast enhancement algorithm achieves good image quality by measuring the results of qualitative and quantitative analyses. To decrease hardware cost and improve hardware utilization for real-time performance, a reduction in circuit area is proposed through use of parameter-controlled reconfigurable architecture. The experiment results show that the proposed hardware-oriented contrast enhancement algorithm can provide an average frame rate of 48.23 fps at high definition resolution 1920×1080. This means that the proposed hardware architecture can run in real-time.