| Summary: | 碩士 === 國立臺北科技大學 === 機電整合研究所 === 100 === Embedded SiGe source/drain technology is an available method to generate the compressive strain in pMOSFETs to increase the hole’s channel mobility. The compressive strain is due to the lattice mismatch between silicon and germanium which makes the silicon in channel to be compressive.
In recent years, the effects of MOSFETs’ performance under different gate lengths and SiGe-S/D have been studied, but the junction leakage of the devices has not been much investigated. In this work, the junction leakage of various gate lengths and widths on the different temperatures (25℃、75℃、125℃) is examined and analyzed. And through the decouple technology with different junction patterns, the fringe junction leakage issue can be effectively extracted and clarified.
The experimental results show that junction leakage of nMOSFETs with silicon cap and SiGe-S/D is much larger than control devices. Therefore nMOSFETs are not included in the scope of this research. On the contrary, the junction leakages of pMOSFETs are in the acceptable range so they are regarded as the major samples. When channel width becomes narrower, the junction leakages of the pMOSFETs are larger. It is presumable that this is due to the strain effect of STI (Shallow trench isolation). Also the junction leakages become grater as the temperature become higher.
Nevertheless, the junction leakages of short channel devices are greater than the long ones. Because small size device is not easy to fabricate and re-filling the SiGe source / drain in small size is more difficult to make, the MOSFET is likely to have defects in the junction, thereby increasing junction leakage current. The MOSFETs with thickness of 39 Å have larger junction leakages than that 24 Å. The reason is that their bonding is not good when the between the silicon of silicon capping layer and silicon germanium of drain. When the covering silicon layer thicker, its drain contact area will become large, then the surface defects would also be more generated. Based on the above conclusions, the ideal silicon capping layer thickness is suggested to be 24 Å.
|
|---|
