| Summary: | 碩士 === 國立臺北科技大學 === 電機工程系研究所 === 100 === Floorplanning is an important and dispensable stage in the traditional integrated circuit design process. With the raised module numbers and increased wire length, the computation complexity is raised dramatically. Obviously, the traditional algorithms need to be updated. We developed an orthogonal table, in which each factor represents a module and the level of a specified factor denotes the orientation of that module. With this orthogonal table, the solution space is significantly decreased.
We use sequence pair to represent a floorplan and the fast longest common subsequence is used accordingly to calculate the area of a floorplan. Different floorplans are generated by perturbation in a simulated annealing process. During simulated annealing, we integrate orthogonal table to scale down the solution space and thus promote the speed of obtaining better solution.
Although the solution space is reduced by orthogonal table, the computation time for deriving the area of each solution is inevitably increased. We use CUDA-based parallel technology to solve this problem.
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