| Summary: | 碩士 === 南台科技大學 === 電子工程系 === 100 === Static random access memory (SRAM) decreases operating voltage with the progress of VLSI process, which results in the reductions of static noise margin (SNM) and read stability the reduction of traditional SRAM Cell, using the same path for reading and writing data can do destroyed the storing data by external noises during the read operation. In this thesis a single bit-line 9T SRAM cell is proposed. This new SRAM cell has the characteristics of high read stability and low power consumption. Due to single bit-line structure in the 9T SRAM cell, the power consumption is better than that of SRAM cells using double bit-lines. Also, the new 9T SRAM cell uses different paths for reading and writing data. The SRAM cell can not be affected by the noise in bit-line during read operation, and therefore has the property of high SNM.
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