Improvement threshold loss problem of low-power full-swing 14-T full adder

• Main Authors: Chen, Chih-Sheng, 陳志昇
• Other Authors: Lee, Po-Ming
• Format: Others
• Language: zh-TW
• Published: 101
• Online Access: http://ndltd.ncl.edu.tw/handle/47456391404799598852

碩士 === 南台科技大學 === 電子工程系 === 100 === In recent years, proposed adder circuit at low power and low transistor counts is the design direction, but most of the low transistor count adders have a threshold voltage loss problem. Hence, consider the design of low power and low transistor counts, overall circuit performance must be considered in the design. This paper proposes two improved threshold voltage loss of low power full swing 14-T full adder circuit. The use of inverter and transmission gate circuits so that the output signal reached full swing states. This paper designs to 8-bit ripple carry adder. To verify the proposed circuits, we compare our circuits with prior circuits. The proposed circuits uses TSMC 0.18μm 1P6M process for simulation of the circuit and chip implementation. Base on the design key point of full swing direction, we propose two 14-T full adder structures and add Low-VTH transistors to improve circuit performance. The proposed circuits solved threshold voltage loss problem. So that the output signal reached full swing states. The simulation results shows that the proposed circuits has a lower power consumption. In addition, a chip is realized to verify overall performance of the proposed circuits.