Reducing the Offset Voltage Effect in a Second-Order Delta-Sigma AD Converter for Audio Frequency Applications

• Main Authors: Ya-Hsin Chou, 周亞忻
• Other Authors: Chia-Yu Yao
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/61218729020448511729

碩士 === 國立臺灣科技大學 === 電機工程系 === 100 === The analog-to-digital converter (ADC) is an important building block in the modern electronic systems. It converts the analog signal into digital form such that it can be processed in a digital signal processing system. There are many different kinds of ADCs. Among them, the ADC that employs the delta-sigma modulator and the oversampling technique pushes the quantization noise to high frequencies and conserves the desired signal at the low frequencies. The quantization noise is therefore easily removed by a low-pass filter. This advantage makes the ADC easily achieve high resolution, especially for audio applications. In this thesis, I design a second-order ADC for audio applications. The offset voltage of the operational amplifier of my circuit is cancelled by the auto-zeroing technique. A novel double sampling technique is used without increasing the clock rate of the converter. Thus, the oversampling ratio is doubled. The resolution of the proposed ADC is 16.19 bits. The circuit is designed in TSMC 1P6M 0.18um CMOS technology. The chip area is 0.99 mm2 and the estimated power consumption of the proposed ADC is 3.92 mW.