| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 100 === This thesis is relevant to the hardware/software co-design and verification of an algorithmic processor for single-pass-based connected component labeling. The research work consists of the following four parts.
The first part of the thesis focuses on the software design for the connected component labeling algorithms. After analyzing the characteristics of the computing results and considering the limitation of physical resources in the embedded systems, single-pass-based connected component labeling algorithms have been developed.
The second part of the thesis focuses on the hardware design for single-pass-based connected component labeling algorithms. A DDR SDRAM is used to store the whole binary input image and the coordinate information of the bounding box of the labeled components. The algorithmic processor comprises four sub-processors: table initializer, labeler, connected component combinator, and connected component information retriever. And, finally, these hardware designs are integrated together and implemented on an Altera FPGA development board.
The third part of the thesis focuses on writing the relevant drivers to construct a verification system for the algorithmic processor. Through using the remote procedure calls this system is controlled to verify the functionality of the processor.
The fourth part of the thesis focuses on the verification and performance evaluation of the whole hardware and software for the algorithmic processor.
Generally speaking, the goal of this thesis is to do the research on the single-pass-based connected component labeling algorithms and algorithmic processors for them are designed and implemented with the Altera FPGA development board. After verifying the algorithmic processors with various types of digital images, it has been shown that the algorithmic processors developed in this thesis have fabulous computing performance. Meanwhile, this approach of hardware/software co-design can also improve the efficiency of both design and verification flows for algorithmic processors.
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