Practical Standard Cell Library Optimizer for Improving Rate of Redundant Via Insertion

• Main Authors: Hung-Ming hong, 洪宏銘
• Other Authors: Shanq-Jang Ruan
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/98434889340520872768

碩士 === 國立臺灣科技大學 === 電子工程系 === 100 === Via failures are an ongoing challenge in nanometer-scale semiconductor manufacturing processes. Adding redundant vias is the standard method for increasing yield and reliability. Cell-based design approaches are extensively adopted for physical implementation. Standard cells (SCs) increase the rate of redundant via1 insertion in cell-based designs. The conventional method for locating pins and tuning pin geometries is manual. This study proposes an e cient pin layout optimizer that considers various con gurations of redundant vias, such as double-vias and rectangle-vias. The proposed method not only solves the problem of the rate of the redundant via1 insertion, but also provides an e ective pin layout checker and optimizer for designing standard cells. To compare the variability of performance and routability in standard cell libraries, accurate characterizations and routing experiments are provided by commercial simulation and routing tools. Furthermore, the proposed standard cell library is implemented easily in all currently available routers. Compared to the conventional SC library, the experimental results reveal that the proposed library improves the total of inserted double-via and total inserted double-via1 by 9.3% and 19.8%, respectively. The proposed scheme also achieves a 26.3% higher redundant via1 insertion rate than conventional approaches and a 100% rectangle-via1 insertion rate.